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preliminary ? 2005 fairchild semiconductor corporation ds500915 www.fairchildsemi.com april 2005 revised may 2005 FIN12AC serdes FIN12AC serdes low voltage 12-bit bi-directional serializer/deserializer with multiple frequency ranges (preliminary) general description the FIN12AC is a 12-bit serializer capable of running a parallel frequency range between 5mhz and 56mhz. the frequency range is selected by the s1 and s2 control sig- nals. the bi-directional data flow is controlled through use of a direction (diri) control pin. the devices can be config- ured to operate in a unidirectional mode only by hardwiring the diri pin. an internal pll generates the required bit clock frequency for transfer across the serial link. options exist for dual or single pll operation dependent upon sys- tem operational parameters. the device has been designed for low power operation and utilizes fairchild pro- prietary low power ctl interface. the device also sup- ports an ultra low power power-down mode for conserving power in battery operated applications. features low power consumption fairchild proprietary low power ctl interface lvcmos parallel i/o interface ? 2 ma source/sink current over-voltage tolerant control signals i/o power supply range between 1.65v and 3.6v analog power supply range of 2.775v r 5% multi-mode operation allows for a single device to operate as serializer or deserializer internal pll with no external components standby power-down mode support small footprint 32-terminal mlp packaging built in differential termination supports external ckref frequencies between 5mhz and 56mhz serialized data rate up to 784mb/s ordering code: pb-free package per jedec j-std-020b. bga and mlp packages available in tape and reel only. p serdes is a trademark of fairchild semiconductor corporation. order number package number package description FIN12ACgfx (preliminary) bga42a pb-free 42-ball ultra small scale ball grid array (uss-bga), jedec mo-195, 3.5mm wide FIN12ACmlx mlp032a pb-free 32-terminal molded leadless package (mlp), quad, jedec mo-220, 5mm square
preliminary www.fairchildsemi.com 2 FIN12AC functional block diagram connection diagram terminal assignments for mlp (top view)
preliminary 3 www.fairchildsemi.com FIN12AC pin description note 1: the dso/dsi serial port terminals have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial connections will properly align without the need for any traces or cable signals to cross. other layout orientations may requir e that traces or cables cross. control logic circuitry the FIN12AC has the ability to be used as a 12-bit serial- izer or a 12-bit deserializer. terminals s1 and s2 must be set to accommodate the clock reference input frequency range of the serializer. the table below shows the terminal programming of these options based on the s1 and s2 control terminals. the diri terminal controls whether the device is the serializer or a deserializer. when diri is asserted low, the device is configured as a deserializer. when the diri terminal is asserted high, the device will be configured as a serializer. changing the state on the diri signal will reverse the direction of the i/o signals and generate the opposite state signal on diro . for unidirec- tional operation the diri terminal should be hardwired to the high or low state and the diro terminal should be left floating. for bi-directional operation the diri of the master device will be driven by the system and the diro signal of the master will be used to drive the diri of the slave device. turn-around functionality the device passes and inverts the diri signal through the device asynchronously to the diro signal. care must be taken by the system designer to insure that no contention occurs between the deserializer outputs and the other devices on this port. optimally the peripheral device driving the serializer should be put into a high impedance state prior to the diri signal being asserted. when a device with dedicated data outputs turns from a deserializer to a serializer the dedicated outputs will remain at the last logical value asserted. this value will only change if the device is once again turned around into a deserializer and the values are overwritten. table 1. control logic circuitry pin name i/o type number of pins description of signals dp[1:12] i/o 12 lvcmos parallel i/o. direction controlled by diri terminal. ckref in 1 lvcmos clock input and pll reference strobe in 1 lvcmos strobe signal for latching data into the serializer ckp out 1 lvcmos word clock output dso / dsi dso / dsi diff-i/o 2 ctl differential serial i/o data signals (note ) dso: refers to output signal pair dsi: refers to input signal pair dso(i) : positive signal of dso(i) pair dso(i) : negative signal of dso(i) pair cksi , sksi diff-in 2 ctl differential deserializer input bit clock cksi: refers to signal pair cksi : positive signal of cksi pair cksi : negative signal of cksi pair ckso , ckso diff-out 2 ctl differential serializer output bit clock ckso: refers to signal pair ckso : positive signal of ckso pair ckso : negative signal of ckso pair s1 in 1 lvcmos mode selection terminals used to define s2 in 1 frequency range for the refclock, ckref diri in 1 lvcmos control input used to control direction of data flow: diri ? 1 ? serializer, diri ? 0 ? deserializer diro out 1 lvcmos control output inversion of diri v ddp supply 1 power supply for parallel i/o and translation circuitry v dds supply 1 power supply for core and serial i/o v dda supply 1 power supply for analog ppl circuitry gnd supply 0 use bottom ground plane for ground signals mode number s2 s1 diri description 0 0 0 x power-down mode 1 0 1 1 12-bit serializer, 20mhz to 56mhz ckref 0 1 0 12-bit deserializer 2 1 0 1 12-bit serializer, 5mhz to 15mhz ckref 1 0 0 12-bit deserializer 3 1 1 1 12-bit serializer, 10mhz to 30mhz ckref 1 1 0 12-bit deserializer
preliminary www.fairchildsemi.com 4 FIN12AC power-down mode mode 0 is used for powering down and resetting the device. when both of the mode signals are driven to a low state the pll and references will be disabled, differ- ential input buffers will be shut off, differential output buffers will be placed into a high impedance state, lvcmos out- puts will be placed into a high impedance state, and lvc- mos inputs will be driven to a valid level internally. additionally all internal circuitry will be reset. the loss of ckref state is also enabled to insure that the pll will only power-up if there is a valid ckref signal. in a typical application mode signals of the device will not change other than between the desired frequency range and the power-down mode. this allows for system level power-down functionality to be implemented via a single wire for a serdes pair. the s1 and s2 selection signals that have their operating mode driven to a ? logic 0 ? should be hardwired to gnd. the s1 and s2 signals that have their operating mode driven to a ? logic 1 ? should be con- nected to a system level power-down signal. serializer operation mode the serializer configurations are described in the following sections. the basic serialization circuitry works essentially identical in these modes but the actual data and clock streams will differ dependent on if ckref is the same as the strobe signal or not. when it is stated that ckref strobe this means that the ckref and strobe signals have an identical frequency of operation but may or may not be phase aligned. when it is stated that ckref does not equal strobe then each signal is distinct and ckref must be running at a frequency high enough to avoid any loss of data condition. ckref must never be a lower fre- quency than strobe. serializer operation: (figure ) modes 1, 2, or 3 diri equals 1 ckref equals strobe the pll must receive a stable ckref signal in order to achieve lock prior to any valid data being sent. the ckref signal can be used as the data strobe signal provided that data can be ignored during the pll lock phase. once the pll is stable and locked the device can begin to capture and serialize data. data will be captured on the ris- ing edge of the strobe signal and then serialized. the serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. when operating in this mode the internal deseri- alizer circuitry is disabled including the ds input buffer. the cksi serial inputs remain active to allow the pass through of the cksi signal to the ckp output. for more on this mode please see the section on passing a word clock. if this mode is not needed then the cksi inputs can either be driven to valid levels or left to float. for lowest power oper- ation let the cksi inputs float. serializer operation: (figure ) diri equals 1 ckref does not equal stobe if the same signal is not used for ckref and strobe, then the ckref signal must be run at a higher frequency than the strobe rate in order to serialize the data cor- rectly. the actual serial transfer rate will remain at 14 times the ckref frequency. a data value of zero will be sent when no valid data is present in the serial bit stream. the operation of the serializer will otherwise remain the same. the exact frequency that the reference clock needs to run at will be dependent upon the stability of the ckref and strobe signal. if the source of the ckref signal imple- ments spread spectrum technology then the minimum fre- quency of this spread spectrum clock should be used in calculating the ratio of strobe frequency to the ckref frequency. similarly if the strobe signal has significant cycle-to-cycle variation then the maximum cycle-to-cycle time needs to be factored into the selection of the ckref frequency. serializer operation: (figure ) diri equals 1 no ckref a third method of serialization can be done by providing a free running bit clock on the cksi signal. this mode is enabled by grounding the ckref signal and driving the diri signal high. at power-up the device is configured to accept a serializa- tion clock from cksi. if a ckref is received then this device will enable the ckref serialization mode. the device will remain in this mode even if ckref is stopped. to re-enable this mode the device must be powered down and then powered back up with ? logic 0 ? on ckref.
preliminary 5 www.fairchildsemi.com FIN12AC serializer operation mode (continued) figure 1. serializer timing diagram (ckref equals strobe) figure 2. serializer timing diagram (ckref does not equal strobe) figure 3. serializer timing diagram using provided bit clock (no ckref)
preliminary www.fairchildsemi.com 6 FIN12AC deserializer operation mode the operation of the deserializer is only dependent upon the data received on the dsi data signal pair and the cksi clock signal pair. the following two sections describe the operation of the deserializer under two distinct serializer source conditions. references to the ckref and strobe signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. when operating in this mode the internal serializer circuitry is disabled including the parallel data input buffers. if there is a ckref signal provided then the ckso serial clock will continue to transmit bit clocks. deserializer operation: diri equals 0 (serializer source: ckref equals strobe) when the diri signal is asserted low the device will be configured as a deserializer. data will be captured on the serial port and deserializer through use of the bit clock sent with the data. the word boundary is defined in the actual clock and data signal. parallel data will be generated at the time the word boundary is detected. the falling edge of ckp will occur coincident with the data transition. the ris- ing edge of ckp will be generated approximately 7 bit times later. when no embedded word boundary occurs then no pulse on ckp will be generated and ckp will remain high. deserializer operation: pwrdwn equals 1 diri equals 0 (serializer source: ckref does not equal strobe) the logical operation of the deserializer remains the same regardless of if the ckref is equal in frequency to the strobe or at a higher frequency than the strobe. the actual serial data stream presented to the deserializer will however be different because it will have non-valid data bits sent between words. the duty cycle of ckp will vary based on the ratio of the frequency of the ckref signal to the strobe signal. the frequency of the ckp signal will be equal to the strobe frequency. the falling edge of ckp will coincident with data transition. the low time of the ckp signal will be equal to ? (7 bit times) of the ckref period. the ckp high time will be equal to strobe period ? of the ckref period. figure is repre- sentative of a waveform that could be seen when ckref is not equal to strobe. if ckref was significantly faster than additional non-valid data bits would occur between data words. figure 4. deserializer timing diagram (serializer source: ckref equals strobe) figure 5. deserializer timing diagram (serializer source: ckref does not equal strobe)
preliminary 7 www.fairchildsemi.com FIN12AC embedded word clock operation the FIN12AC sends and receives serial data source syn- chronously with a bit clock. the bit clock has been modified to create a word boundary at the end of each data word. the word boundary has been implemented by skipping a low clock pulse. this appears in the serial clock stream as 3 consecutive bit times where signal ckso remains high. in order to implement this sort of scheme two extra data bits are required. during the word boundary phase the data will toggle either high-then-low or low-then-high dependent upon the last bit of the actual data word. table provides some examples showing the actual data word and the data word with the word boundary bits added. note that a 12-bit word will be extended to 14 bits during serial trans- mission. bit 13 and bit 14 are defined with-respect-to bit 12. bit 13 will always be the inversion of bit 12 and bit 14 will always be the same as bit 12. this insures that a ? 0 ? o ? 1 ? and a ? 1 ? o ? 0 ? transition will always occur during the embedded word phase where ckso is high. the serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. the deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. the deserializer only uses the embedded word boundary information to find and capture the data. these boundary bits are then stripped prior to the word being sent out of the parallel port. table 2. word boundary data bits lvcmos data i/o the lvcmos input buffers have a nominal threshold value equal to ? of v ddp . the input buffers are only operational when the device is operating as a serializer. when the device is operating as a deserializer the inputs are gated off to conserve power. the lvcmos 3-state output buffers are rated for a source/sink current of 2 mas at 1.8v. the outputs are active when the diri signal is asserted low. when the diri signal is asserted high the bi-directional lvcmos i/ os will be in high-z state. under purely capacitive load conditions the output will swing between gnd and v ddp . the lvcmos i/o buffers incorporate bushold functionality to allow for pins to maintain state when they are not driven. the bushold circuitry only consumes power during signal transitions. figure 6. lvcmos i/o differential i/o circuitry . the FIN12AC employs fsc proprietary ctl i/o technol- ogy. ctl is a low power, low emi differential swing i/o technology. the ctl output driver generates a constant output source and sink current. the ctl input receiver senses the current difference and direction from the corre- sponding output buffer to which it is connected. this differs from lvds which uses a constant current source output but a voltage sense receiver. like lvds an input source termination resistor is required to properly terminate the transmission line. the FIN12AC device incorporates an internal termination resistor on the cksi receiver and a gated internal termination resistor on the ds input receiver. the gated termination resistor insures proper termination regardless of direction of data flow. the relative greater sensitivity of the current sense receiver of ctl allows it to work at much lower current drive and correspondingly a much lower voltage. during power-down mode the differential inputs will be dis- abled and powered down and the differential outputs will be placed in a high-z state. ctl inputs have an inherent fail- safe capability that supports floating inputs. when the cksi input pair of the serializer is unused it can reliably be left floating. alternately both of the inputs can be connected to ground. ctl inputs should never be connected to v dd . when the ckso output of the deserializer is unused it should be allowed to float. figure 7. bi-directional differential i/o circuitry 12 bit data words 12 bit data word with word boundary hexbinaryhexbinary fffh 1111 1111 1111b 2fffh 10 1111 1111 1111b 555h 0101 01010 0101b 1555h 01 0101 0101 0101b xxxh 0xxx xxxx xxxxb 1xxxh 01 0xxx xxxx xxxxb xxxh 1xxx xxxx xxxxb 2xxxh 10 1xxx xxxx xxxxb
preliminary www.fairchildsemi.com 8 FIN12AC pll circuitry the ckref input signal is used to provide a reference to the pll. the pll will generate internal timing signals capable of transferring data at 14 times the incoming ckref signal. the output of the pll is a bit clock that is used to serialize the data. the bit clock is also sent source synchronously with the serial data stream. there are two ways to disable the pll. the pll can be disabled by entering the mode 0 state. (s1 s2 0). the pll will disable immediately upon detecting a low on both the s1 and s2 signals. when any of the other modes are entered by asserting either s1 or s2 high and by pro- viding a ckref signal the pll will power-up and goes through a lock sequence. you must wait specified number of clock cycles prior to capturing valid data into the parallel port. an alternate way of powering down the pll is by stopping the ckref signal either high or low. internal circuitry detects the lack of transitions and shuts the pll and serial i/o down. internal references will not however be disabled allowing for the pll to power-up and re-lock in a lesser number of clock cycles than when exiting mode 0. when a transition is seen on the ckref signal the pll will once again be reactivated. passing a word clock for some applications it is desirable to pass a word clock through the deserializer to the serializer and output it as a reference clock for another device. (see figure ) this can be done under the following conditions: 1. the application mode is unidirectional only. 2. the master word clock is generated on the same side of the cable as the deserializer. to implement pass through functionality on the deserial- izer: 1. diri low 2. ckref low 3. word clock should be connected to the strobe. 4. this will pass the strobe signal out the ckso port. to implement pass through functionality on the serializer: 1. connect ckso of the deserializer to cksi of the serial- izer 2. cksi passes the signal to ckp 3. ckp must be connected to ckref if the word clock being passed through the serializer stops then the serializer must be placed in the reset mode (mode 0) and restarted before the cksi signal will again pass through to ckp. if ckref of the deserializer is running then a high speed bit clock will be passed across the flip instead of strobe. this bit clock will be used as the clock source by the serial- izer provided that no ckref signal exists on the serializer.
preliminary 9 www.fairchildsemi.com FIN12AC application mode diagrams modes 1, 2, 3: unidirectional data transfer figure 8. simplified block diagram for unidirectional serializer and deserializer figure shows the basic operation diagram when a pair of serdes is configured in an unidirectional operation mode. master operation: the device will... (please refer to figure ) 1. during power-up the device will be configured as a serializer based on the value of the diri signal. 2. accept ckref_m word clock and generate a bit clock with embedded word boundary. this bit clock will be sent to the slave device through the ckso port. 3. receive parallel data on the rising edge of strobe_m. 4. generate and transmit serialized data on the ds sig- nals which is source synchronous with ckso. 5. generate an embedded word clock for each strobe sig- nal. slave operation: the device will... 1. be configured as a deserializer at power-up based on the value of the diri signal. 2. accept an embedded word boundary bit clock on cksi. 3. deserialize the ds data stream using the cksi input clock. 4. write parallel data onto the dp_s port and generate the ckp_s. ckp_s will only be generated when a valid data word occurs. figure 9. unidirectional serializer and deserializer
preliminary www.fairchildsemi.com 10 FIN12AC application mode diagrams (continued) figure 10. multiple units, unidirectional signals in each direction figure 11. 8-bit camera interface (10mhz to 30mhz parallel operation) figure shows an 8-bit lcd interface with vsync/hsync capability. this interface is a very straightforward in imple- menting the p serdes devices. note that two additional data bits are still available for implementing additional data bits or control signals. figure shows an application for a camera interface for a flip phone using the FIN12AC. for this application the ref- erence clock is generated on the baseband side of the flip and passed across the serdes pair differentially. this sig- nal is then reconverted to a single ended signal for use as a reference clock by the imager. for some applications it may be possible to connect the refck directly to the ckref signal of the FIN12AC serializer.
preliminary 11 www.fairchildsemi.com FIN12AC absolute maximum ratings (note ) recommended operating conditions note 2: absolute maximum ratings are dc values beyond which the device may be damaged or have its useful life impaired. the datasheet specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. fairchild does not recommend operation outside datasheet specifi- cations. dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. note 3: typical values are given for v dd 2.5v and t a 25 q c. positive current values refer tot the current flowing into device and negative values means current flowing out of pins. voltage are referenced to ground unless otherwise specified (except ' v od and v od ). note 4: typical values are given for v ddp 2.75v and t a 25 q c. note 5: the definition of short-circuit includes all the possible situations. for example, the short of differential pairs to ground, t he short of differential pairs (no grounding) and either line of differential pairs tied to ground. supply voltage (v dd ) 0.5v to 4.6v all input/output voltage 0.5v to 4.6v ctl output short circuit duration continuous storage temperature range (t stg ) 65 q c to 150 q c maximum junction temperature (t j ) 150 q c lead temperature (t l ) (soldering, 4 seconds) 260 q c esd rating human body model, 1.5k : , 100pf ! 2kv machine model, 0 : , 200pf ! 200v supply voltage (v dda , v dds ) 2.775v r 5.0%v supply voltage (v ddp ) 1.65v to 3.6v operating temperature (t a ) (note ) 10 q c to 70 q c supply noise voltage (v dda-pp ) 100 mv p-p symbol parameter test conditions min typ max unit (note ) lvcmos i/o v ih input high voltage 0.65 x v ddp v ddp v il input low voltage gnd 0.35 x v ddp v v oh output high voltage i oh 2.0 ma v ddp 3.3 r 0.3 0.75 x v ddp v v ddp 2.5 r 0.2 v ddp 1.8 r 0.15 v ol output low voltage v ddp 3.3 r 0.3 v i ol 2.0 ma v ddp 2.5 r 0.2 0.25 x v ddp v ddp 1.8 r 0.15 i in input current v in 0v to 3.6v 5.0 5.0 p a i off input/output power-off v ddp 0v, r 5.0 p a leakage current all lvcmos inputs/ outputs 0v to 3.6v differential i/o (note ) i odh output high source current v os 1.0v figure tbd p a i odl output low sink current v os 1.0v figure tbd p a i os short circuit output current v out 0v driver enabled ma driver disabled r 5.0 p a i oz disabled output leakage current ckso, dso 0v to v dds , s2 s1 0v r 1.0 r 5.0 p a i th differential input threshold high current see figure and table 50.0 p a i tl differential input threshold low current see figure and table 50.0 p a i iz disabled input leakage current cksi, dsi 0v to v dds , s2 s1 0v r 1.0 r 5.0 p a i is short circuit input current v out v dds ma v icm input common mode range v dds 2.775 r 5% 0.5 v dds-1 v r trm cksi, ds internal receiver v id 50mv, v ic 925mv, dir i 0 100 : termination resistor |cksi - cksi | v id
preliminary www.fairchildsemi.com 12 FIN12AC power supply currents note 6: the worst case test pattern produces a maximum toggling of internal digital circuits, ctl i/o and lvcmos i/o with the pll opera ting at the refer- ence frequency unless otherwise specified. maximum power is measured at the maximum v dd values. minimum values are measured at the minimum v dd values. typical values are measured at v dd 2.5v. ac specification: serializer timing characteristics over supply voltage and operating temperature ranges, unless otherwise specified. symbol parameter test conditions min typ max units i dda1 v dda serializer static all dp and control inputs at 0v or v dd tbd tbd ma supply current nockref, s2 0, s1 1, dir 1 i dda2 v dda deserializer static all dp and control inputs at 0v or v dd tbd tbd ma supply current nockref, s2 0, s1 1, dir 0 i dds1 v dds serializer static all dp and control inputs at 0v or v dd tbd tbd ma supply current nockref, s2 0, s1 1, dir 1 i dds2 v dds deserializer static all dp and control inputs at 0v or v dd tbd tbd ma supply current nockref, s2 0, s1 1, dir 0 i dds v dda static all dp and control inputs at 0v or v dd tbd tbd ma supply current s1 s2 0 i dd_pd v dd power-down supply current s1 s2 0, 5.0 ua i dd_pd i dda i dds i ddp all inputs at gnd or v dd i dd_ser1 14:1 dynamic serializer s2 h5 mhz tbd tbd ma power supply current ckref strobe s1 l15 mhz tbd tbd (note ) diri hs2 h10 mhz tbd tbd i dd_ser1 i dda i dds i ddp see figure s1 h30 mhz tbd tbd s2 l30 mhz tbd tbd s1 h56 mhz tbd tbd i dd_des1 14:1 dynamic deserializer s2 h5 mhz tbd tbd ma power supply current ckref strobe s1 l15 mhz tbd tbd (note ) diri ls2 h10 mhz tbd tbd i dd_des1 i dda i dds i ddp see figure s1 h30 mhz tbd tbd s2 l30 mhz tbd tbd s1 h56 mhz tbd tbd i dd_ser2 14:1 dynamic serializer nockref 5 mhz tbd tbd ma power supply current strobe o active 15 mhz tbd tbd (note ) cksi 8x strobe 10 mhz tbd tbd i dd_ser2 i dda i dds i ddp diri h30 mhztbdtbd see figure 56 mhz tbd tbd symbol parameter test conditions min typ max units t tcp ckref clock period see figure s2 1s1 0 66.0 t 166 ns (5 mhz - 56mhz) ckref strobe s2 1s1 1 33.0 100 s2 0s1 1 17.8 33.0 f ref ckref frequency relative ckref s2 1s1 0 1.1 * f st 15.0 mhz to strobe frequency does not equal s2 1s1 130.0 strobe s2 0s1 156.0 t tch ckref clock high time tbd 0.5 tbd t t tcl ckref clock low time tbd 0.5 tbd t t clkt lvcmos input transition time figure tbd ns t tch strobe pulse width high figure 5.0 ns t tcl strobe pulse width low figure 5.0 ns f max maximum s2 0s1 1 70.0 210 mb/s serial data rate refck x 14 s2 1s1 0 140 420 s2 1s1 1 420 784
preliminary 13 www.fairchildsemi.com FIN12AC serializer ac electrical characteristics serializer timing characteristics note 7: skew is measured from either the rising or falling edge of the bit clock (ckso) relative to the rising or falling edge of the d ata bit (dso). ckso and dso have been designed to be edge aligned. pll specifications note 8: this jitter specification is based on the assumption that pll has a ref clock with cycle-to-cycle input jitter less than 2ns. note 9: the power-down time is a function of the ckref frequency prior to ckref being stopped high or low and the state of the s1/s2 mo de pins. the specific number of clock cycles required for the pll to be disabled will vary dependent upon the operating mode of the device. deserializer ac electrical characteristics note 10: signals are transmitted from the serializer source synchronously. note that in some cases data is transmitted when the clock re mains at a high state. skew should only be measured when data and clock are transitioning at the same time. total measured input skew would be a combination of output skew from the serializer, load variations and isi and jitter effects. note 11: rising edge of ckp will appear approximately 7-bit times after the falling edge of the ckp output. data will appear coincident with this falling edge. variation with respect to the ckp signal is due to internal propagation delays of the device. note that if ckref is not equal t o strobe for the serializer the ckp signal will not maintain a 50% duty cycle. the low time of ckp will remain in 7 bit times. symbol parameter test conditions min typ max units t tlh differential output rise time (20% to 80%) see figure 19 0.6 0.9 ns t thl differential output fall time (80% to 20%) 0.6 0.9 ns t stc dp[n] setup to strobe diri 12.5 ns t htc dp[n] hold to strobe see figure (f 10 mhz) 0 ns t tccd transmitter clock input to see figure , diri 1, tbd tbd tbd ns clock output delay ckref strobe t sk(p-p) ckso position relative to ds see figure , (note ) tbd tbd tbd ps ckref serialization mode see figure , (note ) tbd tbd tbd no ckref serialization mode symbol parameter test conditions min typ max units t jcc ckso clock out jitter (cycle-to-cycle) (note ) tbd ns t tplls0 serializer phase lock loop stabilization time see figure 1000 cycles t tplld0 pll disable time loss of clock see figure , (note ) 3.0 10.0 us t tplld1 pll power-down time see figure 20.0 ns symbol parameter test conditions min typ max units t s_ds serial port setup time ds to cksi see figure , (note ) 500 ps t h_ds serial port hold time ds to cksi see figure , (note ) 500 ps t rcop deserializer clock output (ckp out) period see figure 23 17.8 t 200 ns t rcol ckp out low time see figure 23 (rising edge strobe) serializer source strobe ckref where a (1/f)/14 (note ) 7a 37a 3ns t rcoh ckp out high time 7a 37a 3ns t pdv data valid to ckp high see figure 23 (rising edge strobe) where a (1/f)/14 (note ) 7a 37a7a 3ns t rolh output rise time (20% to 80%) c l 8pf 3.5 7.0 ns t rohl output fall time (80% to 20%) see figure 3.5 7.0 ns
preliminary www.fairchildsemi.com 14 FIN12AC control logic timing controls capacitance symbol parameter test conditions min typ max units t phl_dir , propagation delay diri low-to-high or high-to-low tbd tbd 10.0 ns t plh_dir diri-to-diro t plz , propagation delay diri low-to-high 7.0 ns t phz diri-to-dp t pzl , propagation delay diri high-to-low 10.0 ns t pzh diri-to-dp t plz , deserializer disable time: diri 0, s1(2) 0 and s2(1) low-to-high 7.0 ns t phz s0 or s1 to dp figure t pzl , deserializer enable time: diri 0, s1(2) 0 and s2(1) low-to-high 10.0 ns t pzh s0 or s1 to dp figure t plz , serializer disable time: diri 1, s1(2) and s2(1) high-to-low 7.0 ns t phz s0 or s1 to ckso, ds figure t pzl , serializer enable time: diri 1, s1(2) and s2(1) low-to-high 10.0 ns t pzh s0 or s1 to ckso, ds figure symbol parameter test conditions min typ max units c in capacitance of input only signals, diri ? 1 ? , s1 0, tbd pf ckref, strobe, s1, s2, diri v dd 2.5v c io capacitance of parallel port pins diri ? 1 ? , s1 0, tbd pf dp[1:12] v dd 2.5v c io-diff capacitance of differential i/o signals diri ? 0 ? , pwndwn 0; tbd pf s1 0, v dd 2.5v
preliminary 15 www.fairchildsemi.com FIN12AC ac loading and waveforms figure 12. differential ctl output dc test circuit note a: for all input pulses, t r or t f 1 ns figure 13. differential receiver voltage definitions figure 14. ?worst case? serializer test pattern figure 15. ctl output load and transition times figure 16. lvcmos output load and transition times
preliminary www.fairchildsemi.com 16 FIN12AC ac loading and waveforms (continued) setup: mode0 ? 0 ? or ? 1 ? m mode1 ? 1 ? , ser/des ? 1 ? figure 17. serial setup and hold time figure 18. lvcmos clock parameters setup: diri ? 0 ? , cksi and ds are valid signals figure 19. deserializer data valid window time and clock output parameters note: ckref signal is free running. figure 20. serializer pll lock time note: strobe ckref figure 21. serializer clock propagation delay figure 22. deserializer clock propagation delay
preliminary 17 www.fairchildsemi.com FIN12AC ac loading and waveforms (continued) figure 23. differential input setup and hold times figure 24. differential output signal skew note: ckref signal can be stopped either high or low figure 25. pll loss of clock disable time figure 26. pll power-down time note: ckref must be active and pll must be stable figure 27. serializer enable and disable time note: if s1(2) transitioning then s2(1) must 0 for test to be valid. figure 28. deserializer enable and disable times
preliminary www.fairchildsemi.com 18 FIN12AC tape and reel specification tape format for uss-bga dimensions are in millimeters note: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). dimensions are in millimeters package a 0 b 0 d d 1 ef k 0 p 1 p 0 p 2 t t c w w c r 0.10 r 0.10 r 0.05 min r 0.1 r 0.1 r 0.1 typ typ r 0/05 typ r 0.005 r 0.3 typ 3.5 x 4.5 tbd tbd 1.55 1.5 1.75 5.5 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3 tape width dia a dim b dia c dia d dim n dim w1 dim w2 dim w3 max min 0.5/ 0.2 min min 2.0/ 0max(lsl - usl) 8 330 1.5 13.0 20.2 178 8.4 14.4 7.9 a 10.4 12 330 1.5 13.0 20.2 178 12.4 18.4 11.9 a 15.4 16 330 1.5 13.0 20.2 178 16.4 22.4 15.9 a 19.4
preliminary 19 www.fairchildsemi.com FIN12AC tape format for mlp mlp embossed tape dimension package tape number cavity cover tape designator section cavities status status leader (start end) 125 (typ) empty sealed mlx carrier 2500/3000 filled sealed trailer (hub end) 75 (typ) empty sealed
preliminary www.fairchildsemi.com 20 FIN12AC physical dimensions inches (millimeters) unless otherwise noted pb-free 42-ball ultra small scale ball grid array (uss-bga), jedec mo-195, 3.5mm wide package number bga042a
physical dimensions inches (millimeters) unless otherwise noted (continued) preliminary 21 www.fairchildsemi.com FIN12AC serdes physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 32-terminal molded leadless package (mlp), quad, jedec mo-220, 5mm square package number mlp032a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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